1. Field of the Invention
The present invention relates to a multicore model simulator.
2. Description of the Related Art
Recently, CPUs have been shifted to multicore designs in built-in processors as in general-purpose CPUs (central processing units) for personal computers. In order to reduce the development period of system LSI which is more and more complicated, it is important to perform co-design of hardware and software from an early stage of design. However, with the existing simulators, multicores cannot be handled, in addition to which, a sufficient simulation speed cannot be obtained. Development of a high-speed software/hardware cooperative simulator becomes a challenge.
FIG. 2 is a diagram showing a main thread (primary thread) 201 of a conventional type simulator. The main thread 201 executes processing 202 of a processor core model PE0 and processing 203 of a processor core model PE1 in loop form. As a result, one main thread 201 is executed as shown in FIG. 1. Note that in FIG. 1, the thick frame represents one thread. In the main thread 201, processing of the processor core model PE0 and processing of the processor core model PE1 are alternately performed. This simulator simulates the two processor core models PE0 and PE1. Simulation is performed with only one processor core, and thus, the processing of the two processor core models PE0 and PE1 are alternately performed.
When a multi-master of multicores, or the like, is simulated with an instruction level simulator (ISS: Instruction Set Simulator), the simulation time multiplies according to the number of cores. For example, when a processor of N of multicores is simulated, it is assumed that the programs executed by the individual processors are the same. When the time taken for one core to execute the program is H seconds, the simulation time of the simulator is N×H seconds because the simulation time is the total time of N of the processors.
Besides, Japanese Patent Application Laid-open No. 2001-318805 describes a test method and a test system for verifying software of a built-in system by building a simulator that simulates a hardware configuration of the built-in system on a computer and by using the simulator.
Besides, Japanese patent Application No. 2004-110812 describes a method and a structure which are capable of effectively mapping memory/address designation of a certain multiprocessing system when emulating by using a virtual memory address designation of another multiprocessing system.
At present, a simulator is used for logic verification of expected value generation and similar aspects of LSI design, further a simulator is used for software application development. Besides, a simulator is used for a simulator for program development of an end user. Because high speed simulators reduce the amount of time required to develop complex LSI designs, there is a need in the simulation art for an improved multi-core simulator.